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FMS7950
Clock Multiplier
Features
* * * * * * * * * Crystal reference input Up to 175 MHz of output frequency Nine configurable outputs Output enable pin 250 pS of output to output skew 300 pS of Cycle to Cycle Jitter VDD Range of 3.3V 0.2V Commercial temperature range Available in 32 pin LQFP
Feedback select (FBsel) pin allows for wider range of input frequencies. When connected low, the lower input frequency range is selected. This provides output frequencies of up to eight times the input (see table 3). The higher input range is allowed when FBsel is connected high. There are four banks of outputs where each bank has a dedicated divide select (DIV_SEL). Depending on the divide selection, the outputs are one half, one quarter, or one eighth of the VCO speed (see table 2 for details). REF_SEL allows selection between crystal input or a clock driven input. Connecting PLL_EN LOW and REF_SEL HIGH will disable the Phase locked loop when the crystal oscillator is not used. In this mode, FMS7950 will be in clock buffer mode where any clock applied to TCLK will be divided down to the four output banks per Table 2. This is ideal for system diagnostic test. FMS7950 operates at 3.3 Volts and is available in 32 pin LQFP.
Description
FMS7950 is a high speed clock synthesizer designed for clock multiplication applications. It uses phase locked loop technology to generate frequencies up to 175 MHz. It has four banks of configurable outputs.
Block Diagram
REF_SEL PLL_EN OE
TCLK QA MUX MUX PLL X1 X2 XTAL OSC QC0 QB
QC1 FBsel QD0 QD1 DIV_SEL A QD2 DIV_SEL B DIV_SEL C DIV_SEL D QD4 Control Logic
QD3
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PRODUCT SPECIFICATION
FMS7950
Pin Assignments
REF_SEL GNDOUT QA VDDOUT GNDOUT PLL_EN TCLK QB
VDDCOR FBsel DIV_SEL A DIV_SEL B DIV_SEL C DIV_SEL D GNDCOR X1
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 32-PIN LQFP 21 20 19 18 17 9 10 11 12 13 14 15 16 VDDOUT QD4 GNDOUT QD3 VDDOUT QD2 X2 OE
QC0 VDDOUT QC1 GNDOUT QD0 VDDOUT QD1 GNDOUT
Pin Description
Pin Name VDDCOR FBsel DIV_SEL(A:D) GNDCOR X1 Pin # 1 2 3, 4, 5, 6 7 8 Pin Type PWR IN IN PWR IN Description Power Connection. Power supply for core logic and PLL circuitry. Connect to 3.3 Volts nominal. Feedback Select. When high, the feedback divide is 8, and when low, it is 16. It allows for a wider range of input frequencies. Divider Select: It divides the clock to a desirable value. See table 2. Ground Connection. Ground for core logic and PLL circuitry. Connect to the common system ground plane. Crystal Connection. An input connection for an external crystal or oscillator. 18 pF internal cap. It can be used as an external crystal connection or as an external reference frequency input. Crystal Connection or External Reference Frequency. This pin has dual functions. Output Enable. When high, all outputs are in high impedance. Normal operation when asserted low. Power Connection. Power supply for all the output buffers. Connect to 3.3 Volts nominal. Clock Outputs. These outputs are multiple of the input. Ground Connection. Ground for all the outputs. Connect to common system ground plane. Test Clock. When REF_SEL is high, all outputs are buffer copy of TCLK. When REF_SEL is low, TCLK is disabled. PLL Enable. When low, PLL is bypassed. Reference Select. When low, crystal is used for input. When high, TCLK is used for input.
X2 OE VDDOUT
9 10 11, 15, 19, 23, 27
OUT IN PWR OUT PWR IN IN IN
QA; QB; QC(0:1); 12, 14, 16, 18, 20, QD(0:4) 22, 24, 26, 28 GNDOUT TCLK PLL_EN REF_SEL 13, 17, 21, 25, 29 30 31 32
2
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FMS7950
PRODUCT SPECIFICATION
Table 1. Functionality
REF_SEL 0 0 0 1 1 1 PLL_EN 0 0 1 0 0 1 OE 1 0 0 1 0 0 PLL By Pass By Pass Enabled By Pass By Pass Enabled All Outputs Hi-Z Running Running Hi-Z Running Running Input XTAL XTAL XTAL TCLK TCLK TCLK
Table 2. Input Versus Output Frequency
FBsel = 1 DIV_SEL A DIV_SEL B DIV_SEL C DIV_SEL D QA QB QC QD QA FBsel = 0 QB QC QD
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
4XRef 2XRef 2XRef 2XRef 8XRef 4XRef 4XRef 4XRef 4XRef 2XRef 2XRef 4XRef 2XRef 4XRef 2XRef 4XRef 4XRef 4XRef 4XRef Ref Ref Ref Ref Ref Ref 2XRef Ref Ref Ref Ref Ref Ref Ref Ref Ref Ref 8XRef 4XRef 4XRef 2XRef 8XRef 4XRef 2XRef 2XRef 8XRef 2XRef 4XRef 2XRef 8XRef 2XRef 2XRef 2XRef 4XRef 4XRef 4XRef 2XRef 4XRef 4XRef 2XRef 2XRef 4XRef 2XRef 4XRef 2XRef 4XRef 2XRef 2XRef 2XRef 2XRef 8XRef 4XRef 2XRef 4XRef
2XRef 2XRef 8XRef 2XRef 4XRef 4XRef 2XRef 8XRef 2XRef 2XRef 4XRef
2XRef 2XRef 2XRef 2XRef 4XRef 4XRef 4XRef 4XRef 2XRef 2XRef 2XRef 2XRef 2XRef 2XRef 2XRef 2XRef 2XRef 2XRef 2XRef Ref Ref Ref Ref Ref Ref 2XRef Ref Ref 2XRef 4XRef 4XRef 2XRef 4XRef
2XRef 2XRef 4XRef 2XRef 4XRef 4XRef 2XRef 4XRef 2XRef 2XRef 4XRef
Note: 1. Reference input could be either crystal input or TCLK input.
Table 3. Divide Select Functionality
DIV_SEL A 0 1 DIV_SEL B 0 1 DIV_SEL D 0 1 DIV_SEL D 0 1 QA /2 /4 QB /4 /8 QC /4 /8 QD /4 /8
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PRODUCT SPECIFICATION
FMS7950
Absolute Maximum Ratings
Symbol VDD, VIN TSTG TB TA Parameter Voltage on any pin with respect to ground Storage Temperature Ambient Temperature Operating Temperature Ratings -0.5 to 7.0 -65 to 150 -55 to 125 0 to 70 Units V C C C
Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may effect reliability.
DC Electrical Characteristics
TA = 0 to 70C; Supply Voltage 3.3 V 0.2V (unless otherwise stated) Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage Input Capacitance(1) Supply Current Clock Stabilization(1) Symbol VIL VIH IIL IIH VOL VOH CIN IDD TSTAB Outputs loaded From VDD = 3.3V to 1% Target VIN= 0 VIN= VDD IOL= 40 mA IOH= -40mA 2.2 7.0 200 10 2.0 -10 -30 10 30 0.5 Conditions Min. Typ. Max. 0.8 Units V V A A V V pF mA mS
Note: 1. Guaranteed by design, not subject to 100% production testing.
AC Electrical Characteristics
TA = 0 to 70C; Supply Voltage VDD = 3.3V 0.2V, CL = 10 pF (unless otherwise stated) Parameter Input Frequency Range Output Frequency Range Symbol FINPUT FOUT Conditions FBsel = 1 FBsel = 0 QA; DIV_SEL A = 0V QB, QC & QD; DIV_SEL B, C, D = 0V Output to Output Skew Rise Duty Time(1) Cycle(1) TSK1 TR TF DT TJIT VTH = VDD/2; DIV_SEL A = 0 VTH = VDD/2; DIV_SEL A = 1 0.8 to 2.0V 2.0 to 0.8V VTH = VDD/2 QA: DIV_SEL A = 0 QA: DIV_SEL A = 1 QB Output QC(0:1) Outputs QD(0:4) Outputs
Note: 1. Guaranteed by design, not subject to 100% production testing.
Min. 25 12
Typ.
Max. 43 22 175 88
Units MHz MHz MHz MHz pS nS nS % pS
400 -300 0.10 0.10 45 100
750 300 1.0 1.0 55 450 200 200 300 375
Fall Time(1) Jitter (Cycle-Cycle)
4
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FMS7950
PRODUCT SPECIFICATION
Parameter Measurement Information
Duty Cycle (DT)
T1 T2 DT = 1.5V 1.5V 1.5V T2 x 100 T1
Rise/Fall Time (TR/TF)
2.0V Output 0.8V 2.0V 0.8V 0V 3.3V
TR
TF
Output to Output Skew (TSK1)
1.5V Q0 1.5V Any Output TSK1
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PRODUCT SPECIFICATION
FMS7950
Application
FMS7950 is one of the simplest form of frequency synthesizer. It uses phase locked loop technology with a divide of "N" in its feedback path. Its purpose is to generate a large number of different output frequencies, all related to a single, highly stable reference source. To achieve this, a crystal is connected at X1 and X2. No external components are required since the capacitors and oscillator are integrated. Figure 1 depicts the block diagram for FMS7950.
X1 Osc. X2
Phase Detected
Loop Filter
VCO
P
QA
Q
QB
R
QC(0:1)
S
QD(0:4)
Figure 1.
In general, phase locked loops are governed by the equation:
F OUT = N * F REF
Equation 1
Equation 1 states that any output can be generated if "N" is varied. In FMS7950, the available dividers are eight or sixteen. These values are selected by connecting FBsel to ground or VDD. To determine the allowable range of input frequencies for each different FBsel setting, the following equation must be used:
F REF = F VCO / N
Equation 2
If divided by eight is selected, the minimum input range will be:
F REF_MIN = 200 / 8 = 25 MHZ
The maximum input range:
F REF_MAX = 360 / 8 = 43.75 MHZ
If divide by sixteen is selected, a lower range of input frequency is allowed (12.5-22MHZ). This analysis reveals that if lower input frequency is available, FBsel must be connected to GND. On the other hand, higher input frequencies require FBsel to be connected to VDD. In practical applications, it is always the output frequency that is known and one must work backwards to determine the input and VCO frequencies. The best approach to explain is by an example. Assume an application requires the following output frequencies:
QA = 133.33 MHZ QB = 66.66 MHZ QC & QD = 33.33 MHZ
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FMS7950
PRODUCT SPECIFICATION
The following connection is used:
DIV_SEL A = 0;P=2 DIV_SEL B = 0;Q=4 DIV_SEL C & D = 1 ; R = S = 8
To calculate the VCO frequency, we find the output that requires the highest frequency and used the following equation. In this case, it will be QA output.
F VCO = P * QA = 2 * 133.33 MHZ = 266.66 MHZ
To determine the input frequency, we will use Equation 2, and set "N" to 16:
F REF = 266.66 MHZ / 16 = 16.66 MHZ
Note, divide by eight could also have been used. The only difference is that it would require an input clock of 33.33MHZ rather than 16.66MHZ.
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PRODUCT SPECIFICATION
FMS7950
Mechanical Dimensions
32-Pin LQFP
Inches Min. A A1 A2 B C D/E D1/E1 e L N ND ccc - Max. 0.063 0.006 0.057 Millimeters Min. - Max. 1.60 0.15 Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions "D1" and "E1" do not include mold protrusion. 3. Pin 1 identifier is optional. 4. Dimension N: number of terminals. 7 5. Dimension ND: Number of terminals per package edge. 6. "L" is the length of terminal for soldering to a substrate. 7. "B" includes lead finish thickness. 2 6 4 5
Symbol
0.002 0.053 0.012 0.018 - 0.004 0.354 BSC 0.276 BSC 0.032 BSC 0.018 0.030 32 8 0 7 - 0.004
0.05 1.35 1.45 0.30 0.45 - 0.10 9.00 BSC 7.00 BSC 0.800 BSC 0.45 0.75 32 8 0 7 - 0.10
D D1
e
E E1
PIN 1 IDENTIFIER C
L .039" Ref (1.00mm)
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C
8
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PRODUCT SPECIFICATION
FMS7950
Ordering Information
Product Number FMS7950KWC FMS7950KWCX Package Description LQFP-32 LQFP-32 w/T+R Package Marking 7950KWC 7950KWC
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 1/9/01 0.0m 005 Stock#DS3007950 2000 Fairchild Semiconductor Corporation

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